1. Field of the Invention
The invention relates to a signal deciding apparatus suitable for use in a semiconductor integrated circuit and, more particularly, to a signal deciding apparatus for converting an AC signal component into a binary digital signal corresponding to the logic levels xe2x80x9c0xe2x80x9dand xe2x80x9c1xe2x80x9d.
2. Related Background Art
FIG. 2 is a circuit diagram showing an example of a conventional signal deciding apparatus.
The signal deciding apparatus has: an input terminal 1 to which an input signal IN is inputted from an outside; and a control terminal 2 to which a control voltage VC for setting a threshold voltage is supplied. Those terminals are connected by a terminating resistor 3 (for example, 50xcexa9). A capacitor 4 (for example, 0.1 xcexcF) for connecting the control terminal 2 to the ground in an AC manner is connected between the control terminal 2 and a grounding voltage GND.
Three cascade connected inverters 51, 52, and 53 are connected to the input terminal 1. An output side of the inverter 53 at the final stage is connected to an output terminal 6. Further, a feedback resistor 7 (for example, 400xcexa9) is connected between the output terminal 6 and control terminal 2. A digital signal OUT corresponding to a desired logic level is outputted from the output terminal 6.
In such an input circuit, when the input signal IN is inputted to the input terminal 1 through a capacitor (not shown), the input signal IN is terminated by the resistor 3 and capacitor 4. Its voltage is inversion amplified by the inverters 51 to 53 of three stages and outputted as a digital signal OUT from the output terminal 6. An average value of the output voltage of the inverter 53 is fed back to the input side of the inverter 51 through an integrating circuit comprising the resistor 7 and capacitor 4 and through the terminating resistor 3.
Thus, if a spread of a noise distribution at the H (high) level of the input signal IN and that of a noise distribution at the L (low) level are almost equal, a duty ratio of the input signal IN is equal to 50% and a threshold value of the signal deciding apparatus can be set to a center voltage as a voltage average value of the input signal IN. Therefore, the preferable output digital signal OUT can be obtained by the signal deciding apparatus. When a deviation occurs between the spread of the noise distribution at the H level of the input signal IN and that of the noise distribution at the L level, the threshold value of the signal deciding apparatus is deviated from the center voltage of the input signal IN, so that it is difficult to accurately decide the H or L level.
In the conventional signal deciding apparatus, therefore, by applying the control voltage VC to the control terminal 2, the threshold value of the signal deciding apparatus can be adjusted in accordance with a change in duty ratio of the input signal IN.
In the conventional signal deciding apparatus, however, the control voltage VC for adjustment of the threshold value is applied as a bias of the input signal IN to the inverter 51 at the front stage through the terminating resistor 7.
Therefore, when the voltage level of the input signal IN decreases, the micro control voltage VC corresponding to the reduction of the voltage level is necessary and the proper threshold value adjustment cannot be easily made.
In case of setting a threshold voltage according to the duty ratio of the input signal IN by applying the control voltage VC to the control terminal 2, if a level of a signal smaller than a discriminatable amplitude of the inverter 51 is inputted as an input signal IN, a duty ratio of the digital signal OUT on the output side largely changes due to such a delicate change of the threshold voltage and there is a problem such that it is difficult to perform a stable control.
It is, therefore, an object of the invention to solve the problems of the conventional technique and to provide an input circuit which can obtain a stable digital signal OUT irrespective of an amplitude and a duty ratio of an input signal IN.
According to a first preferred aspect of the invention, there is provided a signal deciding apparatus comprising: an amplifying circuit which has a plurality of inverting amplifiers that are mutually serially connected and is used for converting an AC input signal into a binary digital signal; and a feedback path which is used for feeding back an output signal of the amplifying circuit to an input signal thereof in order to set a threshold value for binary decision of the amplifying circuit and is equipped with a first integrating circuit for prevention of an oscillation that is caused due to the feedback signal,
wherein the feedback path has: a second integrating circuit for integrating an output signal of one of the inverting amplifiers locating at an odd number stage when it is seen from an input side of the amplifying circuit by a predetermined time constant; a third integrating circuit for integrating an output signal of one of the inverting amplifiers locating at an even number stage when it is seen from the input side of the amplifying circuit by a time constant larger than the time constant of the second integrating circuit; a comparing circuit for comparing output voltages of both of those integrating circuits and supplying an output voltage to the first integrating circuit; and a control circuit for applying a control voltage for setting a threshold voltage to an input terminal of the comparing circuit for receiving the output voltage of the third integrating circuit.
According to a second aspect of the invention, the comparing circuit sets the sum of the output voltage of the third integrating circuit and the control voltage to a threshold value and, when the threshold value is larger than the output voltage of the second integrating circuit, the comparing circuit generates a low level signal to the first integrating circuit, and when the threshold value is smaller than the output voltage of the second integrating circuit, the comparing circuit generates a high level signal to the first integrating circuit.
According to a third aspect of the invention, the amplifying circuit has an even number of inverting amplifiers, the first integrating circuit integrates an input side signal of the inverting amplifier at the final stage, and the second integrating circuit integrates an output signal of the inverting amplifier at the final stage.
According to a fourth aspect of the invention, the first integrating circuit has a time constant which is almost equal to that of the third integrating circuit.
According to a fifth aspect of the invention, the time constant of the second integrating circuit is almost equal to a data period of the input signal.
According to a sixth aspect of the invention, the time constant of the third integrating circuit is hundreds to thousands of times as large as that of the second integrating circuit.
According to a seventh aspect of the invention, the comparing circuit comprises 2n+1 (n is a natural number) operational amplifiers each of which is constructed by mutually serially connecting a depression type field effect transistor and an enhancement type field effect transistor, the 2n operational amplifiers are constructed by serially connecting them to n stages in a manner such that two operational amplifiers whose positive phase (+) sides and negative phase (xe2x88x92) sides are complementarily connected in parallel are used as one set, both outputs of one set of operational amplifiers constructing the set at the final stage of the n-stage connection are inputted to one (2n+1)th operational amplifier for the purpose of comparing them, and a comparison result is inpuutted as an output of the comparing circuit to the first integrating circuit.
According to an eighth aspect of the invention, the input side signal of the inverting amplifier at the final stage of the amplifying circuit is voltage divided into a certain ratio {a/(a+b)} and its voltage division value is inputted to the second integrating circuit. The output side signal of the inverting amplifier at the final stage of the amplifying circuit is voltage divided into a ratio {b/(a+b)} obtained by subtracting the above ratio from 1 and its voltage division value is inputted to the third integrating circuit.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.